At the present time the systems on chip become more and more functional. As soon as the number of elements
is growing linearly, the number of interconnections is growing exponentially. Therefore, the system functional
verification becomes the major task in SoC design processes.
It is scientifically proved that an author can not check more than 85 percent of the project design.
Therefore the functional verification is assigned to separate teams of specialists worldwide.
AlphaCHIP Verification Team:
- has wide experience of functional versification of IP-blocks with various functional purposes and
complexity - from small units to SoCs with a lot of external interfaces;
- the verification process is automated completely; there is not necessity to check time diagrams
visually, therefore, the probability of error omission is minimal;
- there is the verification components library for standard interfaces verification;
- simulation results are saved as separate report files, including statistics on the number of interface
transactions, monitoring of the main processes and parameters, time diagrams recording;
- there is the code coverage statistics: the verification is considered as done at the condition that
the code coverage is not less than 95 percent of RTL-code.
Functional Verification Process consists of the following stages:
- verification plan development and reconciliation with the customer;
- verification environment development, including interfaces functional models, tests, high-level
Verilog-files for simulation and scripts for report files generation;
- system behavior simulation; results analysis, pilot analysis of false situations;
- verification report generation, including the table with test results, quantity (in percent) of
the RTL-code test coverage, RTL-code fragments table which can be never executed.